1. Field of the Invention
This invention relates to a power-on reset system for automatically generating a reset signal when electric power is applied to an LSI.
2. Description of the Related Art
FIG. 8 of the accompanying drawings illustrates a circuit diagram of a typical power-on reset circuit and FIG. 9 is a timing chart for such a circuit.
As shown in FIG. 8, a resistor r and a capacitor c are connected in series between a terminal for power supply voltage VCC and a ground terminal GND, and the input terminal of an inverter is connected to interconnection node A of the devices.
When a power supply voltage is applied to a power-on reset circuit having such a configuration, the node A is electrically charged to show a potential equal to that of the power supply by way of the resistor r. The time required for the charge is a function of the product of the resistance of the resistor r and the capacitance of the capacitor c (time constant). A system reset signal is generated when the potential of node B which is connected to the output terminal of the inverter gets to a predetermined level.
Referring to the timing chart of FIG. 9, as the power supply voltage VCC goes up, the potential of the node A is raised. However, the potential of the node A is level "H" until the potential of the node A reaches a threshold level of the inverter 100. As the potential of the node A goes beyond the threshold level, the potential of the node B is turned to level "L". The period of time during which the node B is set to level "H" is defined as a reset period.
Now, in order to achieve a long reset period with a power-on reset circuit having a configuration as described above, the rise in potential of the node A needs to take place very slowly. This by turn requires a large resistance for the resistor r and a large capacitance for the capacitor c to realize a large time constant, meaning that a physically large resistor r and also a physically large capacitor c having a large surface area need to be used for the circuit to consequently increase the size of the LSI incorporating such a reset circuit. In short, the reset period of the reset circuit incorporated in an LSI of the type under consideration depends on the surface area of the device.
Thus, any known conventional power-on reset circuit is inevitably accompanied by the problem of increase in the size of the LSI incorporating it if the reset period of the circuit is made sufficiently long.